SR latch

Latch is one of the storage device because it can hold data. Latch has two stable states, either its output is at high-state or at low-state. Therefore it is categorized as bistable sequence circuit. In analogy, latch can be viewed as a see-saw diagram below. From the diagram, it has only two stable states which are state1 when set is asserted and state2 when reset is asserted.

bistable states

The most basic and fundamental latch is SR latch. SR latch has two types, they are asserted-high SR latch which is formed by NOR gate and asserted low-SR latch which is formed by NAND gate as shown in the diagram below:

NOR type SR Latch

NAND type SR Latch

Both the latches have SET (S) and RESET (R) input pins but the Nand type SR latch has bar lines above the S and R pins, indicating they are low assertion. The Q and Q are latch outputs, which Q or Q' is always in opposite of the output Q. The characteristic table of SR latch is shown as below:

Characteristic table of SR latch

This table is applicable to both Nand type and Nor type SR latches. SR latch has 3 operating modes, they are hold, reset and set mode. The Qn+1 is to represent the next state of SR latch output while Qn is the current state of SR latch output.

When the SR inputs are 00, the latch is in HOLD mode and maintain its next-state output as Qn.
When the SR inputs are 01, the latch is in RESET mode, hence the next-state output is low, 0.
When the SR inputs are 10, the latch is in SET mode, hence the next-state output is high, 1.
When the SR inputs are 11, what will the output to be? (think...).

By refering to the NOR type (NAND type) circuit diagram, the next-state outputs Q and Q becomes low (high). Therefore this circumstance is contradictory to the statement that Q is always in opposite logic of Q. In other words, this condition violates the equation of Q=not(Q) and thereby this state is not allowed!
The other reason is that it is quite unlikely to insert both the inputs at the exact same time. One of the S or R signal will be arrived earlier.

The symbol of the SR latches are given as below:

NOR-type SR latch (generic SR latch)

NAND-type SR latch

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• Could you convert SR latch to become gated SR latch or clocked SR latch? How?
• Could you distinguish the diferences between latches and flip-flops?

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NOTE:

NAND type SR Latch (the S and R are without bar)

There are some other reference books use different terminology for NAND type SR latch as shown in the figure above. From the figure, the SET (S) and RESET (R) are without bar as compared to the previous figure. Therefore the characteristic table as shown in table below is different from the previous table, which the sequence is inverted. In the other way, you could treat logic low to assert and logic high to deassert the latch. For example, if S=0, R=1, thereby the next-state output is logic 1 or the latch is in set mode.

Characteristic table of NAND type SR latch