3-bit Synchronous down counter with JK flip-flops

This tutorial shows how to design a 3-bit synchronous down counter with JK flip-flops.

Step1:
Construst the state table as below:

State Table

It is clearly that the count-down function has 8 states. In other words, the design is a MOD-8 counter.

This state table does not follow the sequence from low (000) to high (111) but it does follow with the description function of count-down function. It might lead to mistakes when constructing Kmap.

Step2:
Construct JK excitation table since JK flip-flops are used in this design:

JK Flip-Flop

In order to do that, the characteristic of JK flip-flop must be completely comprehended. The diagram below shows the JK flip-flop characteristic, which has 4 modes.

JK Flip Flip Characteristic Table

JK flip-flop is in holding mode and toggle mode when the JK inputs are 00 and 11 respectively. If JK inputs are 01, JK flip-flop is in reset mode, while the inputs are 10, JK flip-flop is in set mode. It behaves almost like SR flip-flop but JK flip-flop has toggle mode.

Excitation Table

You must know how to translate JK characteristic table to JK excitatation table as shown in the table above. It is very crucial to start a design with JK flip-flops.

In what condition, the first row of excitation table 0-->0 is met? By refering to JK charateristic table, the condition can be fulfilled by first and second rows of characteristic table, which JK inputs are 00 and 01. Hence, the J input must be "0" and K input must be "d" (don't care) in the excitation table.

Applying the same concept, JK inputs are "1""d" for the transition from 0 to 1 because of row 3 & 4 of JK characteristic table. (row 4=toggling mode)

JK inputs are "d""1" for the transition from 1 to 0 because of row 2 & 4 of JK characteristic table.
JK inputs are "d""0" for the transition from 1 to 1 because of row 1 & 3 of JK characteristic table.

Step3:
Construct the state table with corresponding excitation table:

With the information from JK excitation table, the state table with corresponding excitation table can be constructed as shown in the first diagram.

State Table and Corresponding Excitation Table (d=don't care)

NOTE: state table only states out the transition from present state to next state without corresponding excitation table. In short, it consists of the first and second columns of the above diagram.

Step4:
Build Karnaugh Map or Kmap for each JK inputs:

Kmap

It will be wise if the present state of the state table follows correct sequence from low (000) to high (111) as the diagram below to avoid silly mistakes happen when transfering from state table with corresponding excitation table to the Kmap. Mistakes do happen!!

state table with correct sequence

Step5:
Draw the complete design as below:

3-bit synchronous down counter with JK flip-flop circuit

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• Could you design a 4 bit synchronous down counter with JK flip-flop circuit?

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The answer as below:

4-bit synchronous down counter with JK flip-flop

• Could you furhter reduce the circuit complexity? how?

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The circuit can be reduced to diagram below:

Reduce the circuit from 3-input AND gate to 2-input AND gate and the routing is much simple.

Simplified 4-bit synchronous down counter with JK flip-flop

• What are the advantages and disadvantages for this circuit that has 2-input AND gate as compared to the previous design which has 3-input AND gate?

• Tips: The answers can be apparent if you think the counter with large bits, eg: 16 bit synchronous counter.

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